1. Field of the Invention
The invention relates to the protection of integrated circuits from electrostatic discharge (ESD), and more particularly to the protection of high voltage NMOS or Drain-Extended NMOS (DENMOS) transistors by a parasitic silicon controlled rectifier (SCR) which triggers at a very low voltage.
2. Description of the Related Art
The protection of integrated circuits from electrostatic discharge (ESD) is a subject which has received a lot of attention from circuit designers because of the serious damage that ESD can wreak as device dimensions are reduced. Workers in the field and inventors have proposed many solutions, many trying to solve the problem of protecting sub-micron devices while still allowing them to function unencumbered and without undue, or zero, increase of silicon real estate. The main thrust of ESD protection for MOS devices is focused on the use of parasitic npn and pnp bipolar transistors, which together form a silicon controlled rectifier (SCR). Unwanted as this SCR normally is, it can safely discharge dangerous ESD voltages as long as its trigger voltage is low enough to protect those MOS devices of which it is a part. The related art as it applies to power output transistors, with particular emphasis on Drain-Extended NMOS (DENMOS) devices for output buffer designs is discussed in a paper by C. Duvvury, J. Rodriguez, C. Jones, and M. Smayling, Texas Instruments Inc., Device Integration for ESD Robustness of High Voltage Power MOSFETs, IEDM 94-407 to 410.
FIG. 1 is a cross-sectional schematic of that paper's high voltage protection device layout and FIG. 2 is the equivalent circuit. FIG. 1 shows a semiconductor wafer 10 with a p-substrate 11 having three n-wells 20, 30, and 40, where n-wells 20 and 30 are NMOS drains. Implanted in the p-substrate are n.sup.+ diffusions 12, 13, 14, 15 and p.sup.+ diffusion 16 (all connected to a reference potential 19, typically ground). n.sup.+ diffusion 21 and 31 are implanted into n-wells 20 and 30, respectively. n.sup.+ diffusion 41 and p.sup.+ diffusion 42 are implanted in n-well 40. Diffusions 21, 31, 41, and 42 are all connected to a voltage supply 18. Tank oxides 22 and 23 straddle n.sup.+ diffusion 21 to either side; similarly, tank oxides 32 and 33 straddle n.sup.+ diffusion 31 to either side. Diffusions 14, 16, 15, 42, and 41 are separated by field oxide regions 17a-d. NMOS (DENMOS) transistor Q3 is formed by items 20, 21, 22, gate 24 and n.sup.+ diffusion 12. NMOS (DENMOS) transistor Q4 is formed by items 20, 21, 23, gate 25 and n.sup.+ diffusion 13. NMOS (DENMOS) transistor Q5 is formed by items 30, 31, 32, gate 34 and n.sup.+ diffusion 13. NMOS (DENMOS) transistor Q6 is formed by items 30, 31, 33, gate 35 and n.sup.+ diffusion 14. The SCR consists of parasitic bipolar pnp transistor Q1 and parasitic bipolar npn transistor Q2 which are formed by p-substrate 11, n-well 40 and diffusions 41, 42 and 15. Resistors R1 and R2 are equivalent resistors for the intrinsic resistance of the n-well 40 and p-substrate 11 material, respectively.
FIG. 2, the equivalent circuit of FIG. 1, shows the typical parasitic SCR comprised of Q1, Q2, R1 and R2. Connected in parallel between voltage supply 18 and reference potential 19 are shown the NMOS (or DENMOS) transistors Q3 to Q6 which are protected by the action of the SCR. The number of NMOS (or DENMOS transistors is not limited to the four shown but depends on the current capacity desired and may be more or less than four.
The problem of the just described device layout is that the SCR is separately implemented by n.sup.+ diffusion 15 and n-well 40, with contacts 41 and 42, as already described. This separate implementation uses up valuable silicon real estate which could otherwise be utilized.
Other related art is described in the following U.S. Patents which propose low voltage lateral SCRs (LVTSCR), modified lateral SCRs (MLSCR), PMOS-trigger lateral SCRs (PTLSCR), NMOS-trigger lateral SCRs (NTLSCR), and modified PTLSCRs and NTLSCRs to control electrostatic discharge:
U.S. Pat. No. 5,745,323 (English et al.) shows several embodiments for protecting semiconductor switching devices by providing a PMOS transistor which turns on when an electrostatic discharge occurs at the output of the circuit.
U.S. Pat. No. 5,754,381 (Ker) provides a modified PTLSCR and NTLSCR, and bypass diodes for protection of the supply voltage and output pad of an output buffer. The trigger voltage is the low snap-back trigger voltage of a short-channel PMOS (NMOS) device.
U.S. Pat. No. 5,754,380 (Ker et al.) is similar to U.S. Pat. No. 5,754,381 above but without bypass diodes. The invention requires a smaller layout area than conventional CMOS output buffers with ESD protection.
U.S. Pat. No. 5,576,557 (Ker et al.) provides ESD protection for sub-micron CMOS devices supplying discharge paths at V.sub.dd and V.sub.ss using two LVTSCRs. In addition a PMOS device is used in conjunction with one LVTSCR and an NMOS device with the other LVTSCR. Inclusion of the PMOS and NMOS devices allows lowering of the trigger voltage to 11-13 Volt.
It should be noted that none of the above-cited examples of the related art provide a combination of low snap-back voltage of less than 2 Volt, high Human Body Model (HBM) ESD Passing Voltage exceeding 8 kVolt and use of an SCR as a protection device without increasing the required real estate area.